1. Field of the Invention
The present disclosure relates in general to non-volatile memories, and more specifically to a system and method for adaptively programming and erasing non-volatile memory.
2. Description of the Related Art
During a typical erase operation of a non-volatile memory (NVM) block, such as electrically erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), block erasable EEPROMs (e.g., “Flash” memories), etc., a preprogram procedure is performed to raise the threshold voltages of the memory cells of the memory block to a level at or above a program verify voltage. For the erase operation, the preprogram procedure is followed by a Fowler-Nordheim (FN) erase procedure to lower the threshold voltages of the memory cells of the memory block to a level at or below an erase verify voltage. During the conventional FN erase procedure, however, the resulting distribution may include memory cells which have been over erased, which results in increased column leakage. Furthermore, the problem of column leakage increases as the memory cells are further scaled, causing, for example, a subsequent program procedure to fail due to lowered drain bias, or a read procedure to fail since the over-erased memory cells may prevent sense amplifiers from distinguishing between an erased cell and a programmed cell. A soft program procedure may be used after the FN erase procedure to compress the distribution of the erased cells so as to reduce the column leakage.
As the technology and feature size of the memory cells become smaller and operating temperatures increase, device leakage is a significant challenge which must be managed to guarantee flash erase and program performance and reliability. Device leakage increases exponentially at higher temperatures, which causes more load on the circuitry within the NVM module and causes performance degradation. Additionally, there is less signal to noise immunity at low voltage due to low voltage drive strength roll-off. With smaller geometries, the transconductance degradation of the memory cell with cycling becomes significant causing a need to manage increasing column leakage throughout the lifetime of the part. For erase procedures, increased high voltage device leakage causes significant loading on the charge pump causing the memory cells to receive very inefficient erase pulse bias levels and may result in a failure to erase. For program procedures, the increased column leakage causes significant loading on the drain charge pumps causing the memory cell to receive very inefficient program pulse bias levels and may result in a program failure.